A Kind of Low Complexity LDPC Decoder
نویسندگان
چکیده
A kind of (1008, 3, 6) rules LDPC decoder was designed in this paper, in order to solving the high complexity of LDPC decoder hardware implementation, which adopted Min-Sum decoding algorithm and partparallel structure. The minimum module in the traditional check function unit (CFU) was improved, which could reduce the complexity of the hardware realization. In the end, the LDPC decoder achieved the desired effect through the comparison of performance analysis, which laid a good foundation for the practical application.
منابع مشابه
High-Throughput and Memory Efficient LDPC Decoder Architecture
Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents a new kind of high-throughput and memory efficient LDPC decoder architecture. In general, more than fifty percent of memory can be saved over conven...
متن کاملA Memory Efficient FPGA Implementation of Quasi-Cyclic LDPC Decoder
Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memor...
متن کاملArchitecture of a low-complexity non-binary LDPC decoder for high order fields
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ≥ 64). The originality of the proposed architecture is that it takes into account the memory problem of the nonbinary LDPC decoders, together with a signif...
متن کاملSearch Based Weighted Multi-Bit Flipping Algorithm for High-Performance Low-Complexity Decoding of LDPC Codes
In this paper, two new hybrid algorithms are proposed for decoding Low Density Parity Check (LDPC) codes. Original version of the proposed algorithms named Search Based Weighted Multi Bit Flipping (SWMBF). The main idea of these algorithms is flipping variable multi bits in each iteration, change in which leads to the syndrome vector with least hamming weight. To achieve this, the proposed algo...
متن کاملAn Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control
A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal ...
متن کامل