Data Security Using Advanced Encryption Standard (aes) in Reconfigurable Hardware for Sdr Based Wireless Systems

A software defined radio (SDR) is a radio transmitter/receiver that uses reconfigurable hardware and software for encoding/decoding, modulation/demodulation, and encrypting/decrypting. This allows much more power and flexibility when designing any radio system. The AES algorithm is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits. The Rijndael cipher has been selected as the official Advanced Encryption Standard (AES) as it is well suited for reconfigurable hardware. The Advanced Encryption Standard can be programmed in software or built with hardware. However Field Programmable Gate Arrays (FPGAs) offer a more customized solution. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented using VHDL as the hardware description language. Here a new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed for software defined radio applications. This system aims at reduced hardware structure and high throughput. Xilinx Project Navigator, ISE 9.1i suite is used for simulation and synthesis.