IJSER - Template

A Delay-Locked-Loop with a quasi-linear modified differential delay element is presented. By employing body feed technique in the bias circuit of delay cell in the Multi-Controlled-Delay-Line, applicable range for the controlled signal has been widen to under-threshold voltages, also the nonlinearity of the conventional current starved delay element the has been suppress by bias circuit. Moreover, improving the noise performance is achieved by taking advantage of the differential structure in the delay cell. The designed circuit has been simulated in ADS software, using TSMC-CM018RF Process with a 1.8V supply voltage. The operating frequency range of the proposed DLL is from 280 MHz to 820 MHz. The maximum and minimum rms jitters are 18 and 4.2 ps, at 280MHz and 820MHz respectively. The maximum power dissipation of designed circuit at 820 MHz is 4.13mW.