Statistical Power Analysis for High-Performance Processors

As device sizes continue to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s processor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload variation, instead of a single number for the average or worst-case power. Unlike statistical timing models that can be represented as a linear canonical form of Gaussian process parameter distributions, the exponential dependency of leakage power on process variables, as well as the complex relationship between switching power and workload fluctuations, present unique challenges in statistical power analysis. This paper presents a comprehensive study on the statistical distribution of dynamic switching power and static leakage power to demonstrate the characterization and correlation methods for macro-level and chip-level power analysis.