Towards Reconfigurable Cache Memory for a Multithreaded Processor

Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today , a reconfigurable device can integrate a large-scale processor and complex hard-wired logic. System designers found that they need a high-performance processor for their reconfigurable device based systems. To improve processor performance , a multithreaded architecture has been introduced; however, performance decreases drastically because of cache misses for shared cache among threads. Moreover, each program that a multithread processor executes may have very different cache access pattern, so that cache optimization for a multithread processor becomes much more complex compared to conventional su-perscalar processors. In this paper, we propose a new cache design which reconfigures cache configuration for each program on reconfigurable device. We found out optimal configuration for each program from designed cache configurations, and estimated improvement rate of reconfigurable cache. The result shows performance gains of 15.12 !s higher than fixed cache design.