Memory Centric Interconnection Mechanism for Message Passing in Parallel Systems

The Interconnection Network (IN) connecting computing nodes in parallel systems has become one of the key research issues in parallel computer architecture. Traditionally, the INs in parallel systems for message passing have been built on the basis of logic circuits with different topology structures. Currently, the bandwidth of data transmission for message passing in available parallel systems reaches the magnitude of Gbps. In this paper, we investigate a kind of interconnection network based on multiport memory for message passing parallel systems, which is termed Memory Centric Interconnection Mechanism (MCIM). The memory is a Multi-Port Fast Static Memory (MPFSRAM) which acts as mailbox for message passing. With considerably simpler Arbitration and Selection Units, MCIM can fully utilize the bandwidth of MPFSRAM for parallel data transfer to achieve the bandwidth of dozen Gbps for message passing with pipelined mode operation of data sending and receiving, meanwhile with much less complexity than that of the IN based on logic circuits, such as routers with hundreds of lines for each link in conventional Mesh structure parallel systems. Furthermore, the buffers in the mail box provide flexible measures for scheduling the message passing. This paper describes the principle of MCIM, the mechanism of data sending/receiving operations, the arbitration/selection of communication path, and the scheduling flowchart of message passing in the buffer. The paper also gives the experimental simulation results of the MCIM performance.