Random Pattern Testing for Sequential Circuits Revisited

Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modiication methods are employed. In this paper we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan ip-ops for a certain length of time instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan ip-ops, the system clock is applied and the primary outputs of the circuit are observed. The number of clock cycles, k, for which each random input is held at a xed value, before applying the next random vector, is determined by using testability analysis or a test pattern generator for a very small number of lines or faults in the circuit. The lines or faults that are analyzed are the primary inputs to ip-ops. The information obtained from the testability analysis or test generator is used to determine the number k of clock cycles for which each random vector is to be held constant without changing the signal values. The algorithm consists of simulating a sequential circuit systematically , possibly with partial scan, in conjunction with the hold method. The method is low cost and the results of our experiment on the benchmark circuits show that it is very eeective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.