Interface Design of VHDL Simulation for Hardware-Software Cosimulation
نویسندگان
چکیده
To perform cosimulation, an interface design of VHDL simulation is needed. This interface is responsible for communicating packets between any VHDL simulator and the cosimulation backplane, PeaCE, which is a Ptolemy extension as codesign environment. The interface also manages the simulation for correct timed cosimulation. By the automatic interface generation mechanism, the interface is generated without user intervention. The proposed interface mechanism is implemented for two VHDL simulators and verified by covalidation with a “QAM-16” modulation example. The results and lessons from the experiment are described.
منابع مشابه
A VHDL-based HW/SW cosimulation of communication systems
In this paper, we introduce homogeneous cosimulation method, which is suitable for modeling and simulation of systems comprising hardware (HW) and software (SW) components. In this method, a hardware description language with embedded programming capabilities (like VHDL) is used to model both HW/SW parts at any desired level of abstraction. Because of platform homogeneity, no sophisticated coor...
متن کاملAutomatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience
This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems pro-totyping applied to an industrial application. The environment provides following features: distributed Hw/Sw cosimulation, automatic Hw/Sw interface generation, Hw elements can be described at different levels of abstraction and generic/specific Sw debuggers can be used. Starting from a b...
متن کاملA Survey of Hw/sw Cosimulation Techniques and Tools Contents
In the last decade, electronic systems have become increasingly complex. The number of func-tionalities built on one chip have risen enormously. To solve the problem of cost and flexibility for such sophisticated, systems the usage of mixed hardware software systems has increased. Due to the complexity, the system development has become more and more difficult and the simulation and evaluation ...
متن کاملAn Integrated Cosimulation Environment for Heterogeneous Systems Prototyping
In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient and convenient verification environment for the rapid prototyping of heterogeneous systems consisting of hardware and software components, the environment supports i) modular cosimulation, ii) cosimulation acceleration, and iii) integrated user interface and internal representa...
متن کاملAn Integrated Hardware-Software Cosimulation Environment for Heterogeneous Systems Prototyping - Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP Intern
In this paper, we present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides interface transparency, simulation acceleration, smooth transition to cosynthesis, and integrated user interface and internal representation. As an experimental example, a...
متن کامل