POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters

While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {−1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.