Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems

An approach to test optimization in switched-capacitor systems based on fault simulation at switch-level is presented in this paper. The advantage of fault simulation at this granularity level is that it facilitates test integration as early as possible in the design of these systems. Due to their mixed-signal nature, both catastrophic and parametric faults must indeed be considered for test optimization. Adequate switch-level fault models are presented. Test stimuli and test measures can be selected as a function of fault coverage. The impact of design parameters such as switch resistance on fault coverage is studied and design parts of poor testability are located. INTRODUCTION The task of testing complex analog and mixed-signal parts in VLSI circuits is rapidly becoming a critical problem during the life-time of these circuits, including prototype, production and maintenance [1]. This is because analog testing has not yet reached the maturity of digital testing. There are no formal approaches that can be exploited to minimize analog testing time and no fault coverage evaluation tools are available [2]. The design of testable analog and mixed-signal VLSI circuits is becoming a must. A testable system lowers integrated circuit (IC) cost by reducing testing time during production, can have an increased field reliability by reducing the chance of early life failures, and can have higher availability by increasing fault coverage and facilitating fault diagnosis. Testability can be increased by taking into account analog design-for-testability (DFT) rules and guidelines, techniques to provide access to deeply embedded analog blocks, or techniques such as built-in self-test (BIST). As for digital circuits, test strategies should be taken into account as early as possible in the design process. During late design stages, circuit redesign for enhancing testability may be very costly. In this paper, we analyze fault coverage in switched-capacitor systems at switch-level through the use of adequate fault models. With respect to previous works, the advantage of evaluating fault coverage at this granularity level is that integration of design and test is considered as early as possible in the design of these systems, and an increase in fault simulation speed of several orders of magnitude is achieved. Besides, we demonstrate in this work how fault coverage figures obtained at switch-level are used for tasks such as: (a) selection of the most adequate test stimuli, (b) determination of circuit parts with poor testability or with unnecessary components, (c) selection of the most adequate test measures and test thresholds, (d) comparison of alternative test approaches, and (e) quantification of impact on fault coverage of design parameters. Previous works dealing with analog fault simulation and testability analysis are first reviewed. Next, our switch-level fault simulation approach and the fault modeling technique are presented. Fault coverage figures are used to analyze testability for the case of a switched-capacitor filter. Finally, some conclusions are provided. TESTABILITY EVALUATION The computation of fault coverage by means of fault simulation has usually been used as a single figure of merit for test exhaustiveness in digital circuits. Fault coverage is defined as a proportion between the number of faults than can be detected (given a certain fault list and a set of input test signals or patterns) and the total number of faults that can occur. Testing has often been considered at gate-level using fault models such as the classical stuck-at model. In the analog domain, fault simulation has been relatively uncommon. One main reason behind this has been a lack of adequate analog fault models which can lead to significative fault coverage figures. The granularity of analog fault simulation has often been limited to transistor-level using catastrophic fault models (like shorts and opens) [3, 4]. Fault simulation and test pattern generation at behavioural-level has only been considered for continuous-time linear analog circuits [5, 6]. In contrast to fault simulation, testability analysis gives a measure of the relative degree of difficulty in testing circuit nodes or key parameters for particular fault models and given test patterns. In the digital domain, this measure has often been based on some mathematical function involving controllability and observability of circuit nodes. In the analog domain, the first published measure of testability is based on determining the solvability of a set of fault diagnosis equations describing relationships between multifrequency measurements and parameters [7]. Algorithms for calculation of this measure have been presented [8, 9]. Other authors use sensitivity values of observable nodes with respect to circuit parameters as a measure of testability with the intention of selecting test frequencies for increasing fault diagnosis [10]. Analog testability analysis has normally been performed at behavioural-level, taking into account functional tests and assuming parametric deviations of circuit components. In [11], fault observability in frequency domain applicable to small-deviation, large-deviation and catastrophic faults is defined as an incremental rather than differential sensitivity at transfer-function level for continuous-time filters. For switched-capacitor systems, fault simulation has normally been limited to transistor-level. Behavioural fault simulations have only been attempted by modeling the discrete-time circuit as an equivalent continuous-time circuit [12, 13]. However, it is known that these models are not correct for all faults that can occur in circuit switches. On the other hand, testability analysis for switchedcapacitor systems using behavioural-level methods is bound to miss large classes of catastrophic faults occurring in this type of systems. Typical faults such as a switch being stuck-on, stuck-open or shorted cannot be adequately modeled at transfer-function level for discretetime circuits. The difficulties for modeling catastrophic faults at behaviourallevel for discrete-time circuits has lead us to consider a fault simulation approach for optimizing circuit testing. This approach is shown in Figure 1. test strategy? can modify test strategy selection test stimuli external test design-for-test approaches input design