Create Better , Faster , Cheaper Designs for FPGAs

With the advent of ever-larger FPGAs, both software algorithm developers and hardware designers must become more productive. Given the frequent lack of resources (time, money, developers) and often unmanageable complexity, today’s complex software systems require an increase in abstraction level. A new generation of methodologies that describe algorithms at a level higher than RTL are collectively called electronic system level (ESL) design tools. ESL enables higher productivity by letting engineers quickly implement their algorithms in hardware. However, many users assume that this is too good to be true, and that the resulting quality of results (QoR) of ESL circuits must be inferior to the best low-level HDL hand designs. This trade-off between productivity and QoR is no longer necessary. In this article, I’ll show you how rapid development using the ESL tool Mobius results in higher productivity, higher performance, and higher quality. I’ll also use as examples the QoR of several FPGA cores implemented with Mobius and compare them to traditional HDL designs. Create Better, Faster, Cheaper Designs for FPGAs