Noise Tolerance Dynamic CMOS Logic Design with Current Mirror Circuit

Dynamic CMOS logic circuits are used in high performance VLSI chips in order to achieve very high system performance. These circuits requires less number of transistors as compare to CMOS logic circuits Dynamic logic circuits are much affected by noise as compared to static CMOS circuit. This is due to the fact that dynamic logic circuits have lower value of switching threshold voltage, which is equal to the threshold voltage of the pull down NMOS devices. On the other hand, switching threshold voltage of static CMOS logic circuit is around half the supply voltage. Our work introduces a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect.