Reconfigurable Image Processing Architecture with Simulink Prototyping Support

A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip (FPGA) with a digital signal processor (DSP). Both these devices have characterics that complement well each other for broad-class of data-intensive imageand video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. At the low level, it has to provide means for hardware setup and runtime re/configuration of the device. At high level, tools for rapid application development are required. The paper describes both the hardware and software architecture of the system and the configuration methods utilized for application development for the proposed architecture.