A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter
نویسندگان
چکیده
A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency. Disciplines Electrical and Computer Engineering Comments Postprint version. Published in Analog Integrated Circuits and Signal Processing, Volume 36, Issue 1-2, July 2003, pages 91-97. The original publication is available at www.springerlink.com. Publisher URL: http://dx.doi.org/10.1023/A:1024410016948 This journal article is available at ScholarlyCommons: http://repository.upenn.edu/ese_papers/153 Paper published in Journal of Analog Integrated Circuits and Signal Processing", July-August 2003, Volume 36, Issue 1-2. pp. 91-97 A FULLY INTEGRATED CMOS PHASE-LOCKED LOOP WITH 30MHZ TO 2GHZ LOCKING RANGE AND ±35PS JITTER Chao Xu, Winslow Sargeant, Kenneth R. Laker, Jan Van der Spiegel Department of Electrical Engineering, University of Pennsylvania 200 S 33rd Street, Philadelphia, PA 19104, USA Email: [email protected] [Abstract] A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-persecond clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.
منابع مشابه
Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter
A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak ...
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