Addressing the Memory Bottleneck in Packet Processing Systems
نویسندگان
چکیده
viii
منابع مشابه
A High Performance Parallel IP Lookup Technique Using Distributed Memory Organization and ISCB-Tree Data Structure
The IP Lookup Process is a key bottleneck in routing due to the increase in routing table size, increasing traıc and migration to IPv6 addresses. The IP address lookup involves computation of the Longest Prefix Matching (LPM), which existing solutions such as BSD Radix Tries, scale poorly when traıc in the router increases or when employed for IPv6 address lookups. In this paper, we describe a ...
متن کاملA High Performance Parallel IP Lookup Technique Using Distributed Memory Organization and ISCB-Tree Data Structure
The IP Lookup Process is a key bottleneck in routing due to the increase in routing table size, increasing traıc and migration to IPv6 addresses. The IP address lookup involves computation of the Longest Prefix Matching (LPM), which existing solutions such as BSD Radix Tries, scale poorly when traıc in the router increases or when employed for IPv6 address lookups. In this paper, we describe a ...
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Active Queue Management (AQM) plays an important role in the Internet congestion control. It tries to enhance congestion control, and to achieve tradeoff between bottleneck utilization and delay. Random Early Detection (RED) is the most popular active queue management algorithm that has been implemented in the in Internet routers and is trying to supply low delay and low packet loss. RED al...
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Active Queue Management (AQM) plays an important role in the Internet congestion control. It tries to enhance congestion control, and to achieve tradeoff between bottleneck utilization and delay. Random Early Detection (RED) is the most popular active queue management algorithm that has been implemented in the in Internet routers and is trying to supply low delay and low packet loss. RED al...
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Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of the buffering and queuing subsystem becomes a significant bottleneck. In high performance routers with more than a few queues, packet buffering is typically implemented using DRAM for data storage and a combination of ...
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