Yoga: A Hybrid Dynamic VLIW/OoO Processor
نویسندگان
چکیده
Out of order (OoO) processors use complex logic to maximize Instruction Level Parallelism (ILP). However, since the resulting dynamic instruction schedule of many applications seldom changes, it is reasonable to store and reuse the schedule instead of reconstructing it each time. To do this, we propose Yoga, a hybrid VLIW/OoO processor that dynamically stores instruction schedules generated while in OoO mode as enlarged basic blocks for future VLIW execution. The enlarged basic blocks are transformed into VLIW words, where the width of the VLIW words corresponds to the ILP found in each block. Yoga switches between OoO mode and VLIW mode, depending on the costs and benefits at each point in time, saving power by turning off OoO structures and unused VLIW lanes when in VLIW mode. Yoga reduces energy consumption by 10% on average, with a maximum of 18%, with negligible performance loss with respect to a conventional OoO processor.
منابع مشابه
A Novel Architecture for Vliw Processor
Technology has seen the development of processor industry right from micro to the latest Nanotechnology with speed being important criteria. Not much attention has been given to the power required to drive these Integrated Circuits. With gaining popularity in mobile computing, developing mobile processors have gained popularity since these processors possess unique properties like low power con...
متن کاملDynamically Scheduling VLIW Instructions with Dependency Information
This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing dynamically scheduled Very Long Instruction Word (VLIW) instructions. Dynamically Instruction Scheduled VLIW (DISVLIW) processor is aimed specifically at dynamic scheduling VLIW instructions with dependency information. The DISVLIW processor dynamically schedules each instruction w...
متن کاملAn eight-issue tree-VLIW processor for dynamic binary translation
Presented is an 8-issue tree-VLIW processor designed for efficient support of dynamic binary translation. This processor confronts two primary problems faced by VLIW architectures: binary compatibility and branch performance. Binary compatibility with existing architectures is achieved through dynamic binary translation which translates and schedules PowerPC instructions to take advantage of th...
متن کاملDynamic Translator: Firmware-Scheduled VLIW Processor
Our group has created a dynamically translating VLIW processor that uses firmware for instruction scheduling. The processor executes MIPS instructions by dynamically translating them into VLIW, and then executing the translated code. We have also implemented a combined toolchain that compiles C to binary for our VHDL processor. The motivation behind the project was to gain practice writing an a...
متن کاملCompiler Processor Tradeoffs for DISVLIW Architecture
The Dynamically Instruction Scheduled VLIW (DISVLIW) processor architecture is designed for balancing scheduling effort more evenly between the compiler and the processor. The DISVLIW instruction format is augmented to allow dependency bit vectors to be placed in the same VLIW word. Dependency bit vectors are added to each instruction format within long instructions to enable synchronization be...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2014