Real-Time Veri cation of Statemate Designs

This paper presents an approach towards real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control units. These embedded control units are usually contained in industrial products and often implement concurrent systems. In our approach designs including all timing information are translated into untimed Kripke Structures which are optimized and then veriied by symbolic model-checking. Real-time requirements are expressed by TCTL formulae interpreted over discrete time. A reduction from TCTL model-checking to CTL model-checking is presented in order to use a CTL model-checker for the veriication task. Some experimental results with the underlying toolset are given.