Improving Bandwidth Utilization using Eager Writeback

Cache memories have been incorporated into almost all modern, general-purpose microprocessors. To maintain data consistency between cache structures and the rest of the memory systems, most of these caches employ either a writeback or a write-through strategy to deal with store operations. Writethrough caches propagate data to more distant memory levels at the time each store occurs, producing a significant bus traffic overhead to maintain consistency between the memory hierarchy levels. Writeback caches can significantly reduce the bandwidth requirements between caches and memory by marking cache lines as dirty when stores are processed and writing those lines to the memory system only when that dirty line is evicted. Writeback caches work well for many applications; however, for applications that experience significant numbers of cache misses over a very short interval due to streaming data, writeback cache designs can degrade overall system performance by clustering bus activity when dirty lines contend with data being fetched into the cache. In this paper we present a technique called Eager Writeback, which avoids performance loss due to clustered memory traffic patterns found in streaming and graphics applications by speculatively ”cleaning” dirty cache lines prior to their eviction. Eager Writeback can be viewed as a compromise between write-through and writeback policies, in which dirty lines are written later than write-through, but prior to writeback. We will show that this approach can effectively avoid the performance degradation caused by clustering bus traffic in a writeback approach, while incurring very minimal additional memory traffic.