Design Issues of the Parallel Delta - Sigma A / DConverterEric

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of L th-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of 2, 4, and 8 second-order delta-sigma modulators is described that does not require over-sampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is veriied. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to non-ideal circuit behavior characteristic of the individual delta-sigma modulators.