Timing Extensions and Simulation
نویسندگان
چکیده
In this paper the Signal Transition Graph (STG) model { a speci cation form that is widely used for asynchronous circuits' behavior speci cation is extended to allow the delay information specifying. Timed STG models and their ring semantics are dened. Then we present an automatic technique for timed STG behavior specifying in VHDL. The resulting VHDL speci cation may be used to simulate STG behavior with the speci ed delays. The requirements imposed on the STG to allow the joint environment { circuit behavior simulation are de ned. Joint simulation of a circuit synthesized from STG with its environment is also presented.
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