Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz
نویسندگان
چکیده
A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146μW at 1.5V supply.
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