Combining Local and Global History for High Performance Data Prefetching

In this paper, we present our design for a high performance prefetcher, which exploits various localities in both local cache-miss streams (misses generated from the same instruction) and the global cache-miss address stream (the misses from different instructions). Besides the stride and context localities that have been exploited in previous work, we identify new data localities and incorporate novel prefetching algorithms into our design. In this work, we also study the (largely overlooked) importance of eliminating redundant prefetches. We use logic to remove local (by the same instruction) redundant prefetches and we use a Bloom filter or MSHRs to remove global (by all instructions) redundant prefetches. We evaluate three different design points for the proposed architecture, trading off performance for complexity and latency efficiency. Our experimental results based on a set of SPEC 2006 benchmarks show that we improve performance (over 1.6X for our highest performance design point) for various processor configurations, which model different cache capacity and memory access bandwidth.