A Bottom-Up Approach to On-Chip Signal Integrity
نویسندگان
چکیده
We present a new approach to accurately evaluate signal integrity in digital integrated circuits while working at the logic level. Our approach makes use of fitting models to represent the key properties of drivers, interconnects and receivers and the effects of all noise sources (supply noise, timing uncertainty, crosstalk). Such models are then combined to evaluate the correctness of each bit sent across the line. The overall result is a parameterized bit-level model of a noisy on-chip communication channel. The model can be used at the logic level to evaluate the transmission-error probability for an arbitrary bit stream, sent at an arbitrary bit rate, under arbitrary noise source assumptions.
منابع مشابه
A Comparative Study of Effect of Bottom-up and Top-down Instructional Approaches on EFL Learners’ Vocabulary Recall and Retention
This quasi-experimental study investigated the effect of bottom-up and top-down instructional approaches on English as a foreign language (EFL) vocabulary recall and retention. To this end, 44 high school students from two intact classes were assigned to bottom-up (n = 21) and top-down (n = 23) groups. The participants were exposed to 20 hours of explicit vocabulary instruction during 10 weeks ...
متن کاملAn On-Chip Spectrum Analyzer for Signal Integrity Estimation of High Speed Serial Links
We present an on-chip spectrum analyzer (OSA) to estimate signal integrity of high speed serial links. The proposed OSA is composed of an on-chip sine-wave generator (OSG) and an on-chip amplitude detector (OAD), which are physically implemented in a four-metal, 1.8 V, 0.18 um standard CMOS technology. The implemented OSA is experimentally verified with a characterization of High-Definition Mul...
متن کاملFine Control of Local Whitespace in Placement
In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout ...
متن کاملProceedings Template - WORD
Swaroop Ghosh Computer Science and engineering, University of South Florida, Tampa, Florida-33647 [email protected] ABSTRACT We propose a path to achieve an ambitious target that has never been tried before: a terabyte of on-chip memory for petabit/second of bandwidth with < 5W of power. Conventional methodology of on-chip memory design is bottom up where the choice of bitcell topology and ass...
متن کاملA Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs
The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for st...
متن کامل