A wireless embedded sensor architecture for system-level optimization

Emerging low power, embedded, wireless sensor devices are targeting a wide range of applications, yet have very limited processing, storage, and energy resources. An architecture must be developed that can efficiently meet system demands while simultaneously remaining flexible to application specific optimizations. Analysis of past designs identifies core architectural issues and their impact on system performance. This paper outlines these issues and presents a generalized architecture designed to provide efficient communication mechanisms while allowing for system-level optimizations. The importance of providing a tight coupling between application and communication processing is shown and the tradeoffs associated with virtual versus physical parallelism are investigated. We conclude that a shared controller closely integrated with special-purpose hardware accelerators is the preferred building block for a flexible yet efficient node. A subset of the architecture is implemented using commercial building blocks and shows substantial improvements in communication performance and the ability to perform system-level optimizations that obtain tight synchronization and low power channel monitoring.