Adaptive Parallel Computation for Blind Source Separation with Systolic Architecture

The purpose of Blind Source Separation (BSS) is to obtain separated sources from convolutive mixture inputs. Among the various available BSS methods, Independent Component Analysis (ICA) is one of the representative methods. Its key idea is to repetitively update and calculate the measures. However, dealing with the measures obtained from multi-array sensors causes obstacles for real-time use. In order to solve this problem, it is necessary to convert the software implementation of BSS algorithm into the hardware architecture. Through the use of hardware architecture, the BSS algorithm can efficiently work within a relatively short time. In this study, we investigate a practical method using a parallel algorithm and architecture for hardware use in a blind source separation. We design a feedback network for real-time speech signal processing. The network is composed of forward and updates algorithms. The architecture of the network is systolic and therefore it is suitable for parallel processing. We only have to add and connect modules for scaling. This paper covers the process from the systolic design of BSS to the hardware implementation using Xilinx FPGAs. The simulation results of our proposed implementation are also represented in the experimental section. In that section, our architecture returns satisfying results with robust qualities.