Massively Parallel Inner-Product Array Processor

We present a hardware architecture for parallel innerproduct array computation in very high dimensional feature spaces, towards a general-purpose kernel-based classiJer and function approximator: The architecture is internally analog with fully digital interface. On-chip analog jinegrain parallel processing yields real-time throughput levels for high-dimensional (over 1,000per chip) classification tasks. The architecture contains an array of computational cells with integrated digital storage and a parallel bank of analog-to-digital converters (ADC). A three-transistor unit cell combines a single-bit dynamic random-access memory (DRAM) and a charge injection device (CID) binary multiplier and analog accumulator: Digital multiplication with enhanced resolution is obtained with bit-serial input vectors and bit-parallel storage of weights, by combining quantized outputs from multiple rows of binary unit cells over time. A prototype 128 x 512 inner-product array processor on a single 3mm x 3mm chip fabricated in standard CMOS 0.5pm technology achieves 8-bit effective resolution, consumes 3.3mW of power and offers 2 x 10l2 binary MACS (multiply accumulates per second) per Watt of power: This corresponds to a factor of at least 1,000 increase in computational efficiency compared to modem desktop workstations. Based on the inner-product array processor, an ejicient real-time massively-parallel hardware architecture of a Support Vector Machine classifier is presented.