Modeling and extraction of interconnect capacitances for multilayer VLSI circuits

We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method extraction of the complete circuit level capacitances at each node in the circuit. The layout geometry is reduced into base elements that consist of different vertical profiles at each node in the layout. Accurate analytical models are developed for calculating capacitances of structures using a 2-D capacitance simulator TDTL. These are then transformed into 3-D geometry. The resulting capacitance are found to be within 10% of both the measured data and 3-D simulations of structures that are prevalent in a typical chips. The models and their coefficients for different vertical profiles are stored in the capacitance extraction tool CUP, which is coupled to the layout extractor HILEX. As each base element has a unique vertical the corresponding capacitance can be calculated for each node that is then written out to a circuit The comparisons of the models with the measured dam, as well as 3-D simulations results, are also discussed. Conductor 2