A Fast-Locking Analog PLL With Deskew Buffer
نویسنده
چکیده
In this paper, PLL are most frequently used for Local Oscillator (LO) signal generation in wireless radio transceivers to down convert the carrier frequency to lower or intermediate frequency . The input reference frequency is 6.4 MHz. The architecture used for the design of Frequency synthesizer was Integer-N architecture. This was designed using 0.25 μm technology. The VCO designed was a CMOS differential LC tuned oscillator. Phase noise for the design. A frequency divider with a divider ratio of 100 was implemented. The programmable prescaler architecture was used for designing the divider and the latches for each cell were designed using Current Mode Logic. A nand gate based Phase Frequency detector was designed along with the charge pump. A third order loop filter was used for the design. The design of frequency synthesizer was implemented in Tanner tools. The application for which the frequency synthesizer will be designed is for Radiosonde which is used for weather forecasting.
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