New Queuing Strategy for Large Scale ATM Switches

In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to determine the buffer requirements needed to achieve a given Quality of Service (e.g., a given cell loss probability). Based on this study, we propose a Combined Central and Output Queuing (CCOQ) technique to be used in designing large-scale ATM switches. Also, we propose a general design technique for an NxN lurge-scale ATM switch with a suitable CCOQ buffer size to reduce both the cell loss probability and the complexity o f the memory modules. The switch has to be designed such that it can be implemented using the smallest number of VLSI chips possible. It should be also reliable for commercial use. The switch should support multicast and priority controlfunctions. 1. Combined Central and Output Queuing (CCOQ) For large-scale ATM switches (in terms of input and output ports), the amount of memory that needs to be installed in the switch is large, so reducing the size of the memory is of great importance. In many cases, the amount of memory that needs to be installed in a large-scale ATM switch is large and it can not be integrated on a single chip either because of its size or because of the lower operating speed that it will have. In such cases and based on our simulation studies, we propose to implement the large-scale ATM switch out of smaller switches where a small amount of memory needs to be installed in each of these smaller switches. This technique will slightly increase the total amount of memory that will be used to implement the large-scale ATM switch. But, a number of other advantages of this approach can be listed as: The amount of memory that needs to be integrated on a single switch is small. The operating speed of these smaller memories installed in the small switches that make up the largeAla I. AI-Fuqaha Research and Development Princeton Optical Networks, Inc. gmpls@yahoo. com scale ATM switch is more than that of one large memory. Using this approach, the design of the switch will be more modular. The number of output ports of the switch can be increased at any time by adding smaller switches inside the large-scale ATM switch. 2. Performance of CCOQ Figure 1 shows different buffering configurations that can be used within a 16x16 ATM switch. These configurations include output buffering, shared buffering, and two other Combined Central and Output Queuing (CCOQ) configurations in which all the input ports and part of the output ports have access to the same memory module. Table 1 shows the number of memories, size of memory integrated on a single chip, and the total memory needed in all of these configurations. The table shows that in case of shared buffering, the amount of memory that needs to be integrated on a single chip is 600*424 bits. In case of output buffering, the table shows that the amount of memory that needs to be integrated on a single chip is 150*424 bits but 16 of these memories are needed. Studying Table 1, we conclude that the two CCOQ configurations (with M=2 and M=4) are better than the output buffering configuration in terms of the total memory that needs to be installed in the switch. The table also shows that the two CCOQ configurations are better than the shared buffering configuration in terms of the amount of memory that needs to be integrated on a single chip. Figure 2 shows that when the number of memories used in the switch (16x16 in this example) increases from one to two and then to four, the amount of memory that needs to be integrated on a single chip decreases dramatically. When the number of memories used in the switch is more than four, we only see a slight decrease in the buffer size that needs to be integrated on a single chip. Thus, using four memory modules for a 16x 16 switch to achieve 1 0-5 cell loss probability is a good selection in this example, assuming that the most critical design condition is the amount of memory to be integrated on a single chip and the speed of this memory. 43 0-7695-1092-2/01 $10.00