Remote Store Programming: Mechanisms and Performance

This paper presents remote store programming (RSP). This paradigm combines usability and efficiency through the exploitation of a simple hardware mechanism, the remote store, which can easily be added to existing multicores. Remote store programs are marked by fine-grained and one-sided communication which results in a stream of data flowing from the registers of a sending process to the cache of a destination process. The RSP model and its hardware implementation trade a relatively high store latency for a low load latency because loads are more common than stores, and it is easier to tolerate store latency than load latency. This paper demonstrates the performance advantages of remote store programming by comparing it to both cache-coherent shared memory and direct memory access (DMA) based approaches using the TILEPro64 processor. The paper studies two applications: a two-dimensional Fast Fourier Transform (2D FFT) and an H.264 encoder for high-definition video. For a 2D FFT using 56 cores, RSP is 1.64× faster than DMA and 4.4× faster than shared memory. For an H.264 encoder using 40 cores, RSP achieves the same performance as DMA and 4.8× the performance of shared memory. Along with these performance advantages, RSP requires the least hardware support of the three. RSP’s features, performance, and hardware simplicity make it well suited to the embedded processing domain.