μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS
نویسندگان
چکیده
An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent selfcalibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-quality keys with measured Shannon entropy up to 0.99999999995 and lower-bound min-entropy >0.99. The 100% digital design enables a compact layout occupying 1088μm, with scalable operation down to 300mV, while passing all NIST statistical randomness tests.
منابع مشابه
A robust -40 to 120°C all-digital true random number generator in 40nm CMOS
An all-digital True Random Number Generator (TRNG) harvesting entropy from the collapse of 2 edges injected into one even-stage ring is fabricated in 40nm CMOS. A configurable ring and tuning loop provides robustness across a wide range of temperature (-40 to 120°C), voltage (0.6 to 0.9V), process variation, and external attack. The dynamic tuning loop automatically configures the ring to meet ...
متن کاملSPICE Simulation of a "Provably Secure" True Random Number Generator
In their paper “A Provably Secure True Random Number Generator with Built-in Tolerance to Active Attacks”, B. Sunar, W. Martin, and D. Stinson propose a design for a true random number generator. Using SPICE simulation we study the behaviour of their random number generator and show that practical implementations result in a too high frequency signal to be processed with current CMOS technology.
متن کاملISSCC 2015 / SESSION 17 / EMBEDDED MEMORY AND DRAM I / O / 17 . 1 17 . 1 A 0 . 6 V 1 . 5 GHz 84 Mb SRAM
The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a des...
متن کاملA Fully-Digital Chaos-Based Random Bit Generator
In this paper, the design of a fully-digital chaos-based random bit generator (RBG) is reported. The proposed generator exploits a chaotic system whose map is implemented in the time domain where the state variables of the system are represented by the phase of digital ring oscillators. This results in an extremely robust and e cient entropy source which can be implemented as a digital standard...
متن کاملFPGA Implementation of Metastability-Based True Random Number Generator
True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in freerunning ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability ...
متن کامل