Comparator Circuits over Finite Bounded Posets

Comparator circuit model was originally introduced in [5] (and further studied in [2]) to capture problems which are not known to be P-complete but still not known to admit efficient parallel algorithms. The class CC is the complexity class of problems many-one logspace reducible to the Comparator Circuit Value Problem and we know that NLOG ⊆ CC ⊆ P. Cook et al [2] showed that CC is also the class of languages decided by polynomial size comparator circuits. We study generalizations of the comparator circuit model that work over fixed finite bounded posets. We observe that there are universal comparator circuits even over arbitrary fixed finite bounded posets. Building on this, we show the following : • Comparator circuits of polynomial size over fixed finite distributive lattices characterizes CC. When the circuit is restricted to be skew, they characterize LOG. Noting that (uniform) polynomial sized Boolean circuits (resp. skew) characterize P (resp. NLOG), this indicates a comparison between P vs CC and NLOG vs LOG problems. • Complementing this, we show that comparator circuits of polynomial size over arbitrary fixed finite lattices exactly characterizes P and that when the comparator circuit is skew they characterize NLOG. This provides an additional comparison between P vs CC and NLOG vs LOG problems. The lattice that we design to prove this result is non-distributive and cannot be embedded into any distributive lattice preserving meets and joins. • In addition, we show a characterization of the class NP by a family of polynomial sized comparator circuits over fixed finite bounded posets. As an aside, we consider generalizations of Boolean formulae over arbitrary lattices. We show that Spira’s theorem[6] can be extended to this setting as well and show that polynomial sized Boolean formulae over finite fixed lattices capture exactly NC. These results generalize the results in [2] regarding the power of comparator circuits. Our techniques involve design of comparator circuits and finite posets. We then use known results from lattice theory to show that the posets that we obtain can be embedded into appropriate lattices. Our results gives new methods to establish CC upper bound for problems also indicate potential new approaches towards the problems P vs CC and NLOG vs LOG using lattice theoretic methods. ∗Supported by TCS PhD Fellowship