Code Compression Algorithm for High Performance Micro Processor

Modern processors use two or more levels of cache memories to bridge the rising disparity between processor and memory speeds. Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memory. Accessing off-chip memory generally takes an order of magnitude more time than accessing on-chip cache, and two orders of magnitude more time than executing an instruction. Compression can improve cache performance by increasing effective cache capacity and eliminating misses. Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and all work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware .In this paper a lossless compression algorithm designed for fast on-line data compression, and cache compression in particular is proposed. The algorithm has a number of novel features tailored for this application, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. The algorithm is proposed to a register transfer level hardware design, permitting performance, power consumption, and area estimation. The cache compression is evaluated using full-system simulation and a range of benchmarks. It can be shown that compression can improve performance for memory-intensive commercial workloads.