Specification of Control Flow Properties for Verification of Synthesized VHDL Designs

Behavioral speciications in VHDL contain multiple communicating processes. Register level designs synthesized from these speciications contain a data path represented as a netlist and a controller consisting of multiple communicating synchronous nite state machines. These nite state machines together implement the control ow speciied in and implied by the behavioral speciication in VHDL. This paper describes a systematic approach to identifying the control ow properties critical to the proper functioning of designs synthesized from VHDL. These properties are then formulated as speciications in Computational Tree Logic (CTL) while presenting a controller model for high-level synthesis. These speciications form a necessary set that must be satissed by any correct synthesized design. A high-level synthesis system, as a byproduct of creating RTL designs, can automatically generate these CTL speciications. 1 Motivation VHDL, the vhsic hardware description language admits behavior level specii-cations of systems containing multiple communicating processes. A high-level synthesis system accepts such behavioral speciications and produces register transfer level (RTL) designs. An RTL design usually comprises a data path and a nite state controller. The controller can be conveniently organized as a set of hierarchical, communicating synchronous state machines 1]. In VHDL, process communication and synchronization is achieved by signal assignment statements and wait statements. When a process encounters a wait statement it suspends until the wait predicate is satissed. When all processes suspend, signals can be updated using their projected values stored on transaction lists 2]. The process of verifying a synthesized RTL design can be accomplished by two basic approaches: simulation and formal veriication. In the simulation based approach , the behavioral speciication is simulated using a set of carefully selected ?