HOE for clock distribution in integrated circuits : Experimental results
نویسندگان
چکیده
This paper reports the design and fabrication of transmission holographic optical elements (HOEs) for clock distribution. First, we have studied and fabricated a multi-focus doublet HOE. The aberrations due to the wavelength shift between recording (= 488 nm) and reconstruction ( = 780 nm) have been minimized by an appropriate recording and readout geometry. The diffraction efficiency has been optimized by a copying technique. Second, we have investigated the near-field internal reflection (TIR) holographic recording technique to solve the problems of miniaturization. With this method, we have recorded a lOOxlOO lenlet array with focal lengths of f =400 jim.
منابع مشابه
Clock Distribution Networks in Synchronous Digital Integrated Circuits
Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relativ...
متن کاملHigh-Frequency Clock Distribution Methods in Digital Integrated Circuits
This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.
متن کاملTiming and area optimization for standard-cell VLSI circuit design - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
AbstructA standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient algorithm for combinational circuits, we exa...
متن کاملDesign of Resonant Clock Distribution Networks for 3-D Integrated Circuits
Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing ...
متن کاملTiming and area optimization for standard-cell VLSI circuit design
A standard cell library typically contains several versions of any given gate type, each of which has a di erent gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an e cient algorithm for combinational circuits, we examine the pr...
متن کامل