Investigation on ESD Robustness of CMOS Devices in a 1.8-V 0.15-μm Partially-Depleted SOI Salicide CMOS Technology

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process. INTRODUCTION SOI (Silicon-on-Insulator) is expected as a promising technology for advanced ULSI in terms of high speed and low power dissipation. But, ESD reliability in sub-quarter-micron SOI CMOS technology becomes a challenge due to the low thermal conductivity of the buried oxide underneath the top layer silicon film and the STI (Shallow-Trench-Isolation) structure on the insulating layer [1]. When the circuit design transiting from bulk to SOI CMOS process, some new ESD protection designs with the Lubistor diode or B/G-coupled MOS in the thin film SOI technology had been reported [2]. However, an output buffer in the SOI CMOS process is still often formed by a pull-up PMOS and a pull-down NMOS, which are directly connected to the bond pad. The ESD overstress voltage zapping to the output pin of a CMOS IC is conducted to the output PMOS and NMOS. Therefore, the output PMOS and NMOS still need to be designed and carefully drawn in layout to sustain a reasonable ESD stress. ESD level of commercial IC products is generally requested to be higher than 2kV in HBM ESD stress [3]. Thus, the device characteristics in a new SOI CMOS process still need to be investigated in details for defining one set of design rules for on-chip ESD protection design. Table I Gate OxideThickness (thin, for 1.8V) 26 Å NMOS/PMOS Threshold Voltage (Vtn/Vtp) 0.45V/0.5V Buried Oxide (BOX) Thickness 1000 Å Silicon Thickness on BOX 1500 Å n+, p+ Doping Concentration 10~10 cm N-well, P-well Doping Concentration 5E17 cm In this work, both NMOS and PMOS with four different device structures and different layout parameters have been fabricated in a 0.15-μm partially-depleted SOI salicide CMOS process to verified their ESD robustness. The effectiveness of ESD clamp circuit designed with the gate-driven or the substrate-triggered techniques in this 0.15-μm partiallydepleted SOI salicide CMOS process is also investigated. P-s u b s t r a t e B u r i e d O x i d e S T I S T I N + N + P -w e l l S D B