JIFFY - ein FPGA-basierter Java Just-in-time-Compiler für eingebettete Anwendungen

The steadily growing performance of processors for embedded systems make the usage of the platform independent Java system more and more attractive. However, the usual techniques known for acceleration of the Java Virtual Machine, widely used on desktop computers, don’t apply well in general to this class of devices, the most prominent example is the Just-in-Time-Compilation (JIT). This is caused by the tight resource constraints of these systems and their wide range of processor architectures. This thesis presents the JIFFY concept, which describes the integration of a complete JIT-compiler for the JVM into an Field Programmable Gate Array (FPGA). By using the FPGA, a very high translation speed can be achieved, the code quality and thus execution speed reaches or exceeds simple, software based JITs. Based on a layered concept, the translation process in the FPGA und therefore the synthesized gate logic is independent of the target CPU architecture. This feature allows a very flexible usage of the FPGA even for heterogenous multiprocessor systems, typically found in modern communication applications. Besides the detailed explanation of the translation process itself, the impacts of the FPGA-based approach on the Java runtime system and possible considerations in the implementation of the hardware and software are also described. To qualify and quantify the resulting properties for CISC and RISC CPUs, the system is modeled for two typical architectures (80586 and AlphaCPU).