A Comparison of Software and Hardware Synchronization Mechanisms for Distributed Shared Memory Multiprocessors

E cient synchronization is an essential component of parallel computing The designers of traditional multiprocessors have included hardware support only for simple operations such as compare and swap and load linked store conditional while high level synchronization primitives such as locks barriers and condition variables have been implemented in software With the advent of directory based distributed shared memory DSM multiprocessors with signi cant exibility in their cache controllers it is worthwhile considering whether this exibility should be used to support higher level synchronization primitives in hardware In particular as part of maintaining data consistency these architectures maintain lists of processors with a copy of a given cache line which is most of the hardware needed to implement distributed locks We studied two software and four hardware implementations of locks and found that hard ware implementation can reduce lock acquire and release times by compared to well tuned software locks In terms of macrobenchmark performance hardware locks reduce appli cation running times by up to on a synthetic benchmark with heavy lock contention and by on a suite of SPLASH benchmarks In addition emerging cache coherence protocols promise to increase the time spent synchronizing relative to the time spent accessing shared data and our study shows that hardware locks can reduce SPLASH execution times by up to if the time spent accessing shared data is small Although the overall performance impact of hardware lock mechanisms varies tremendously depending on the application the added hardware complexity on a exible architecture like FLASH or Avalanche is negligible and thus hardware support for high level synchro nization operations should be provided This work was supported by the Space and Naval Warfare Systems Command SPAWAR and Advanced Research Projects Agency ARPA Communication and Memory Architectures for Scalable Parallel Computing ARPA order B under SPAWAR contract N C