New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

نویسندگان

  • S. Wairya
  • R. K. Nagaria
  • S. Tiwari
چکیده

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature. Keywords—Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

متن کامل

Comparative Performance Analysis of XOR- XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS...

متن کامل

Transistor-Level Optimization of Three Input XOR/XNOR Gate Using CMOS Logic Design

Power consumption and delay are two important considerations for VLSI systems. prime motive of this project is to reduce the power and to get less delay that is nothing but the high speed for any design. So Adder is one of the fundamental blocks present in arithmetic logic unit (ALU), floating point unit. Adders are very important components in some other applications such as microprocessor and...

متن کامل

A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits

ABSTRACT : In this paper, we review various design techniques for XOR-XNOR circuits as these circuits are basic building blocks of many arithmetic circuits. The XOR and XNOR circuits can be implemented in different architectures by using different circuit designs. This paper evaluates and compares the performance of various design techniques of XOR-XNOR circuits. The performance of the XOR-XNOR...

متن کامل

Design of high speed and low power 5:3 compressor architectures using novel two transistor XOR gates

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2012