Real-Time Debugging by Minimal Hardware Simulation

This paper describes a debugging environment for real-time applications that supports the querying of the elapsed time at break-points. The environment employs hardware simulation at the level of processor cycles. The hardware simulation is limited only to the aspects relevant to processor cycle accounting and includes instruction caching, instruction frequency accounting, and instruction pipelining. This simulation is performed by program instrumentation to minimize the performance impact. Thus, the environment provides the means to debug a real-time application for an embedded system on a regular workstation in an eecient manner.