Yield Learning Simulation

نویسنده

  • Pranab K. Nag
چکیده

In this paper, a method to predict defect-related yield as a function of time for a semiconductor manufacturing facility is presented. The effect of contamination-related defects on yield, and the reduction in defect levels, resulting from failure analysis, have been considered. The developed yield learning model is incorporated in a prototype simulator ,Y4 ,which mimics both the fabrication and the failure analysis processes. Results are presented for a spectrum of examples to illustrate the use of the simulator, in formulating IC manufacturing strategies.

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تاریخ انتشار 1998