An Analog Architecture for Split-Radix DHT
نویسندگان
چکیده
The fast Hartley transform and algorithm for DHT was introduced by Bracewell. The split radix decimation-infrequency algorithm that requires less number of operation counts as compared to the radix-2 and radix-4 algorithms was developed by Sorenson et al. In this paper, an analog architecture for a split radix decimation-in-time algorithm is proposed. It utilizes three different structures in the signal flow diagram. It exhibits a recursive pattern and is modular. The validity of the analog architecture is tested by simulating it with the help of the Orcad PSpice. General Terms Analog architecture, Discrete Hartley transform
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