Link Pipelining for an Energy-Efficient Asynchronous Network-on-Chip

Wire latency across the links of a NoC potentially limit available bandwidth, especially in deep submicron technology. Pipeline buffers may be placed on long links to increase throughput and flit buffering. In asynchronous (clockless) NoCs, this can be done to only those links that will yield benefits, and is especially useful in heterogeneous embedded SoCs with irregular layouts and traffic. We evaluate two strategies that determine where link pipeline buffers should be placed in the topology. The first compares available link bandwidth, based on physical wirelength, to the throughput needed by each sourceto-destination path, for each link. The second adds buffers to a link such that its bandwidth at least matches the throughput of a core’s network adapter. These strategies were integrated into our network optimization tool for an application-specific SoC. Simulations used its expected traffic patterns, floorplan-derived wirelengths, and self-similar traffic generation for more realistic behavior. Results show improved large-message network latency and network adapter output buffer delay. There was a slight power increase with the addition of pipeline buffers, but our proposal is a complexity-effective improvement by the power-latency product metric. The strategy of pipelining certain links based on their expected traffic provides a more efficient performance increase compared to solely a traffic-oblivious addition of buffers.