Low Power and Small Area Implementation for OFDM Applications

This paper proposes that several FFT algorithms such as radix2, radix-4 and split radix were designed using VHDL with the multiplication complexity reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers and the simulations of standard 0.35 μm. The sizes of FFT/IFFT operations are varied in different applications of OFDM systems. The reorganized Mixed Radix 4-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition execution is our suggested VLSI system architecture to design the module FFT/IFFT processor for OFDM systems. The output shows that the proposed processor architecture can minimize the area cost while keeping a high-speed processing speed, a decrement of more than 70% of the power consumption/area when compared with complex multiplier.