Computationally Efficient Sub-module Selection Scheme for Voltage Balancing Controller of Modular Multilevel Converter

SUMMARY Modular multilevel converter (MMC) type topology is considered an enabling technology for expanding the voltage sourced converter (VSC) applications and thus providing its operational benefits with low switching power loss comparable to that of the conventional thyristor-based line commutated converters. However, due to its inherent topological and consequently control complexity, computational efficiency of the algorithms for fully simulating and then implementing the features of MMC are always pursued. MMC uses a stack of identical converter sub-modules, providing a step in the multilevel waveform, and the number of sub-modules may increase to more than 200 for the high power applications. Selection of the sub-modules set to be switched in or out, thus controlling and balancing the capacitor voltage for realizing the best performance at each control instant, may be the most crucial but time-consuming functions as well. Implementation steps of these functions are briefly discussed below: Generate reference signals for determining how many sub-modules in total are to be in the on-state condition at each control instant. This is called modulation process. Next select the sub-modules to be in. Note again that this process is for controlling the capacitor voltage of individual sub-modules. By balancing the capacitor voltage of each sub-module, it is possible to optimally utilize the stored energy and evenly distribute power losses to the installed electrical devices while avoiding concentration of thermal stress on specific sub-modules, which harmfully affects the life span of each sub-module and the reliability of the MMC. Prior research efforts for designing voltage balancing controller have relied on sorting algorithm: individual capacitor voltages are first measured and are then sorted by their magnitudes. In case of positive arm current, the sub-module with the lowest voltage level is selected to charge its capacitor. In case of negative arm current, the sub-module with the highest voltage is selected to supply the output voltage level. This may be a straightforward way for selecting the sub-modules. However, as the number of sub-module increases for high voltage applications, the computational intensity to sort the capacitors increases: Note that it may require more than 200 sub-modules for the HVDC system and heavy computation should be a great challenge. Two representative sorting algorithms are considered in this study, i.e., bubble and quick sorting algorithms. Bubble sorting method takes computational time in the order of O(n 2) theoretically. Quick sort requires computational time of O(nlogn) on average. 1 For the state-of …