The Effect of Local Buffer Memory Size on FDDI Throughput

The effect of the size of local buffer packet memory on the throughput of FDDI adapters is examined. The analysis focuses on transmit buffer size and covers both the loaded and unloaded FDDI ring cases. A hypothetical EISA FDDI adapter design is used as a vehicle to demonstrate the throughput characteristics of different local buffer memory sizes. Calculations are done to size the buffer with respect to the latency of the EISA bus for the card in a target system configuration and with respect to the amount of effective bandwidth that the card can expect to receive. It is demonstrated that sizing a buffer based on these two methods results in poor throughput when the FDDI ring is loaded. As a solution to the performance problem, it is suggested that buffer sizing based on the TTRT value of the ring will result in an adapter that is capable of realizing high throughput. Finally, the AMD SUPERNET 2 FDDI chipset is examined to show that it is able to meet a diverse set of buffer sizing needs.