A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
نویسندگان
چکیده
Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.
منابع مشابه
A BIST Structure to Test Delay Faults in a Scan Environment
When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...
متن کاملAging Monitoring Methodology for Built-In Self-Test Applications
The high integration level, complexity and performance achieved in new nanometer technologies make IC (Integrated Circuits) products very difficult to test. Moreover, long-term operation brings aging cumulative degradations, and new processes and materials lead to emerging defect phenomena. The consequence is obtaining products with increased variability in their behavior, more susceptible to d...
متن کامل‘Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST’, IEEE Transactions on Very Large Scale
The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose...
متن کاملSwitching Activity Reduction Using Scan Shift Operation
This paper presents BIST TPG (built in self test) for low power dissipation and high fault coverage a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG subside transitions...
متن کاملAnalysis of Two Pattern Test Cubes for Transition Path Delay Faults in Digital Circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses the concept of sensitizing cubes introduced in an earlier paper and a new, more efficient algorithm for generating them. Sensitizing cubes of the next state and output logic are used to obtain static sensitizing vectors...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- J. Electronic Testing
دوره 14 شماره
صفحات -
تاریخ انتشار 1999