Design and Implementation of Low Power Multiplier Using Vedic Multiplication Technique
نویسندگان
چکیده
DESIGN AND IMPLEMENTATION OF LOW POWER MULTIPLIER USING VEDIC MULTIPLICATION TECHNIQUE Aniruddha Kanhe1, Shishir Kumar Das1 and Ankit Kumar Singh2 1Department of Electronics and Telecommunication Engineering NIT Raipur, India, E-mail: [email protected], [email protected] 2Department of Computer Science and Engineering NIT Raipur, India, E-mail: [email protected] In this paper a low power Multiplier is presented. The multiplier implemented here is based on the ancient Vedic Multiplication Technique. The Urdhva-tiryakbhyam and Nikhilam sutras are used for multiplication. The multiplier based on ancient technique is compared with the modern multiplier to highlight the power and speed advantages in the Vedic Multipliers. The Vedic Multiplier is tested by using BIST (Built In Self Test) and it is found Fault free. The results are compared with the Booth's Multiplier in terms of time delay and power. The high speed processor requires high speed and low power multipliers and the Vedic Multiplication technique is very much suitable for this purpose.
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