Establishment of Secured Communication

The main objective of this project is handling the large numbers of faults in F.P.G.A. configurable logic blocks. A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. A challenging aspect of developing applications that target the interfacing of the processor with the surrounding reconfigurable logic is main criteria in this project. O.C.P protocol interfaces the embedded processor with F.P.G.A. Testing all configurable logic blocks is under care of embedded processor. The embedded processor set the test mode for F.P.G.A, when it is needed it stops when it is in sleep mode. INTRODUCTION: ADVANCES in silicon technologies continue to increase the number of transistors that can be integrated into a single device. Many chip manufacturers use this new integration potential to fabricate complete systems on a single silicon device. FPGA manufacturers are using this expanded capacity to implement embedded DSPs, multipliers, and memory blocks along with the reconfigurable fabric. At Xilinx, FPGA designers have developed new generations of FPGA architectures that contain a variety of embedded resources. the processor core is that most FPGAs contained within an embedded system require some level of interaction with an external processor. Moving this processor onto the FPGA chip eliminates bottlenecks associated with communicating through off-chip interfaces. These are replaced by on-chip interfaces that must provide efficient communication between the processor andthe reconfigurable resources. Since direct human intervention for maintenance and repair is impossible in such environments, fault-tolerant (FT) techniques resulting in graceful degradation must be used to achieve the desired mission life span even in the presence of faults. Existing technique: Only offline testing is available in FPGAs,there is no control over the testpatterns implies there is no accuracy while the circuit is in running position. Offline testing Deals with testing a system when it is not carrying out its normal functions (Test mode, Non-Real-Time error detection).There are two types of offline testing. Structural : Execution based on the structure of the CUT(Explicit fault model LFSR, ...). Functional : Running based on functional description of CUT(Functional fault model Diagnostic software) PROPOSED BLOCKDIAGRAMS: By using above block diagram we can develop a ONLINE BIST, Since there is an interaction of embedded processor.