Virtual Testing Method for Static Adc Non-linearity – Rsd Cyclic A/d Converter Case

− One of the recent approaches to test A/D converter performance is the so-called Servo-Loop Method. This method is aimed at the non-linearity extraction of static ADC transfer curve. In this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistorlevel example of the Residual Signed Digit (RSD) cyclic A/D converter design. The background of the considered Servo-Loop version was proposed in [1]. In this paper, we establish a Virtual Testing Environment (VTE) built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.